ASICs (application specific integrated circuits) are widely used by electrical design engineers to include specialized circuitry in their designs using only a single chip. The term “ASIC” actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, module based arrays, and gate arrays. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate and/or customize.
In forming ASICs generally, several layers will be required. FIG. 1 shows a cross-sectional view of a generic integrated circuit. First, active layers are formed on a semiconductor substrate. The active layers 110 include devices such as transistors and diodes. Most active layer devices are formed independently of one another, i.e., they are not connected to form a circuit. Thus, once active layers 110 are formed, conducting layers, which are often composed of a metal such as aluminum or copper but can be formed with other conductors, are formed over the active layers to interconnect the devices, thereby forming a circuit. Several metal (or other conducting) layers maybe required to completely interconnect the devices to form a useful circuit. Four metal layers, M1 120, M2 130, M3 140 and M4 150, are shown in FIG. 1. Of course, different types of ICs may require more or less than four metal layers for circuit interconnection.
In between each metal layer is an insulating layer 115, 125, 135, 145 as shown in FIG. 1. Insulating layers are present to prevent shorts between metal layers. To interconnect the metal layers, vias 116 are formed through the insulating layers.
In forming the structure of FIG. 1, after the active layers 110 are formed, an insulating layer 115 is formed over the active layers 110, for instance, by growth or deposition of insulating material. Next, a masking step is utilized to form vias in the insulating layer, as is generally known in the art. Such masking often entails depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching the insulating layer in accordance with the photoresist pattern. After forming the vias, a metal layer is deposited and then patterned using a similar masking process, so that metal remains only in desired locations. The process is repeated for each insulating layer and metal layer required to be formed.
Thus each metal layer required to be formed generally demands at least two masking steps: one step to form vias through the insulating layer to connect to the layer below and one step to form connection wires or lines. Unfortunately, each mask step required generally entails significant time and expense.
At the active layer level, ASIC active devices are generally arranged to form an array of function blocks, also commonly referred to as cells or modules. To interconnect active devices within each function block (i.e., form “local interconnections”) a series of horizontal and vertical connection lines formed in the metal layers are utilized. As is well understood in the art, any two points can be connected using a series of horizontal and vertical connection lines. While such local interconnections can be done in one metal layer, more typically, horizontal connections are formed in a first metal layer and vertical connections are formed in a second metal layer with an insulating layer having vias formed between.
As should be understood and as used herein, “horizontal” is meant to describe all metal lines running in a first direction such that all horizontal lines lie substantially parallel to one another. “Vertical” is meant to convey all lines that run in a second direction which is substantially perpendicular to the first (horizontal) direction. Neither “horizontal” nor “vertical” is meant to convey anything more specific than relative position to one another. Moreover, as should be understood by those of skill in the art, horizontal lines and vertical lines are formed in the metal layers which are parallel to the active layer surface. “Horizontal” and “vertical” do not convey lines that are perpendicular to the active layer surface.
The local interconnections within each function block described above are typically quite dense, and often function blocks themselves must be connected together (i.e., circuit or global “routing”). Yet routing in lower metal layers over function blocks is often impractical due to the large number of obstructions formed by the local interconnections in those lower layers. Therefore, in order to form connections between the function blocks, routing has typically been done “around” the function blocks and will be discussed below with respect to FIGS. 2-3.
The Channeled Approach
One function block routing solution is shown in FIG. 2, showing a generalized plan view of a standard cell-type ASIC. As shown, in a standard cell, each function block 160 (160a-160i) will vary in horizontal size with respect to one another (although they are typically structured to have the same vertical height). Function blocks 160 are shown with dashed lines to indicate their conceptual formation in active layers 110. As discussed above and as shown in function block 160d, local interconnections within each function block are typically formed by horizontal lines in M1, e.g., 174, 176, and vertical lines in M2, e.g., 178. The horizontal and vertical lines are connected in their respective layers by vias, shown as “dots.” Vias may not only connect M1 and M2 to each other but may also connect M1 and/or M2 to an active layer.
The function blocks 160 are further formed into rows 170a, 170b, 170c. Each row is separated from one another by a “channel” region 172a, 172b. The channel region is then used for horizontal routing between function blocks to avoid routing over the function block space. For instance, referring to FIG. 2, channel lines 180-182 and 184-186 are formed in channels 172a and 172b, respectively, using M1. Vertical lines 190-199 are formed in M2. Vertical lines 190-193 are used to couple the active devices in function block 160d to channel lines. The channel lines in turn are further connected (in M2) to other function blocks, e.g., with vertical lines 194-199. As shown, the channel lines can run the entire length of the channel or can run for a short distance within the channel.
Vias in the function block are connected to channel lines with connector lines that enter from above the function block, e.g., line 192, from below the function block, e.g., line 193, or double entry (connected from above and below), e.g., lines 190, 191. Lines could also simply “feed-through” the function block with no connection to a via; however, feed-throughs are often impractical because of dense local interconnections within the function blocks, limiting routing flexibility.
Gate arrays, like standard cells, have also used an approach as described above with reference to FIG. 2. That is, gate arrays have also been fabricated with channels to use for routing between function blocks. In gate arrays, however, the active layers are fixed (non-customizable), having a predefined number and arrangement of active devices in each function block. Thus, while fully-customizable standard cells can customize channel size larger or smaller, in gate arrays the channel size is fixed, further limiting routing flexibility.
In summary, the “channel” technique described with respect to FIG. 2, conventionally does all routing among function blocks in the channel regions. The only M1 metal outside of each function block (i.e., not used for local interconnections) is located in the channel regions, between rows of function blocks.
The Channel-less Approach
Another approach often used for routing interconnections among gate array function blocks and described with reference to FIG. 3 is a “channel-less” approach. Each function block 302 (302a-302i) is substantially contiguous to adjoining function blocks on each side—in other words, no routing channels are formed. Using substantially contiguous function blocks can increase the functionality available per IC since no fixed space is wasted for channels. Like the “channeled” approach, local interconnections within each function block are still typically formed with horizontal and vertical connections using M1 and M2, respectively, such as shown in function block 302g. Nonetheless, routing among function blocks is still restricted in that routing lines cannot always cross over the used function block space due to the local interconnect density. Therefore, typically in the channel-less structure of FIG. 3 routing is also done over selectively unused function blocks. Occasionally, even whole rows of function blocks are selectively unused in order to allow routing much like a channeled device, although more commonly only individual function blocks are selected to be reserved for routing, e.g., function blocks 302d and 302e. 
The Time-Space Factors
Because of limitations in the metalization process, typically only a few metal layers have been used for routing conventionally. Nonetheless, recent developments in metalization and planarization technologies, particularly in the area of chemical-mechanical polishing (CMP), have allowed more metal layers to be formed. Still, in each of these techniques described above, both channeled and channel-less, considerable customized routing (for both standard cell and gate arrays) is done in the M1 and M2 layers. Additional customized layers are also often used. Therefore, at least four masking steps (two for each metal layer) are required to form a customized circuit. Yet, as previously mentioned, each custom mask step will take considerable time and money.
Often important to an IC or electronic circuit designer is customization time. Particularly during the design stages, the engineer may want to obtain a model, or prototype, of his or her designs quickly so that the designs can be tested with other circuitry. In such circumstances, the engineer may opt for a gate array because, although not as flexible as standard cells, it will be faster to get a working chip because fewer mask steps are required for circuit customization (i.e., standard cells require formation of active devices, while gate arrays have preformed active devices and only require metalization). Nonetheless, gate arrays can still take several weeks' time or much longer to obtain because of the multiple custom mask steps that must be performed just for metalization.
Further, it is generally important to the design engineer to obtain the smallest chip possible containing the maximum amount of functionality. Using a channeled scheme, space used for channels obviously takes away real estate that could otherwise be used for more function blocks or, if removed, would reduce IC size. Of course, using the channel-less scheme described above, otherwise usable function blocks are often unusable. While some companies have gone so far as to develop techniques that require only one mask step for customization, thus reducing turn-around time, almost all of these companies have continued to use channel regions, increasing IC size and/or reducing IC functionality and routing flexibility. Clearly then, any customizable circuit that can decrease turn-around time while simultaneously maintaining a high degree of functionality and routing flexibility is desirable.